1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a flattened wiring structure of an elevated wiring density, a semiconductor device with a coaxial wiring structure, a method for producing such semiconductor devices, a method of forming contact between a semiconductor electrode and a silicon substrate, and a method of forming a through-hole in a multi-layered wiring structure.
2. Related Background Art
Initially the following is an explanation of the method of producing a conventional example of a semiconductor device, with reference to FIGS. 1B and 1A, which are respectively a plan view of the semiconductor device and a cross-sectional view along a line A--A' in FIG. 1B.
On a semiconductor substrate 55 already bearing functional elements thereon, BPSG (boron phosphosilicate glass) or PSG (phosphosilicate glass) is deposited with a thickness of 6000-8000 .ANG. for example by CVD to form a first insulation layer 53. Then contact holes 56, for connecting the semiconductor substrate 55 with first wirings 51, are opened by patterning. The etching in this operation is usually conducted with a mixture of fluorine gas and chlorinated gas, anisotropically in the direction of depth.
Then Al (or an Al alloy) is deposited with a thickness of 0.6-1 .mu.m over the entire surface, for example by magnetron sputtering, and an etching operation with Cl-containing etching gas is conducted to form the first Al wiring layer 51 into desired patterns. Subsequently PSG, or a silicon nitride film formed by plasma CVD, is deposited over the entire surface, thereby obtaining an insulation layer 54 of a thickness of 5000-8000 .ANG..
Subsequently through-holes 57 are opened by patterning of photoresist and etching with a fluorine/chlorine-containing gaseous mixture. Then aluminum is deposited with a thickness of ca. 0.8-1.2 .mu.m over the entire surface again with the magnetron sputtering apparatus, and second wirings 52 are formed with a desired pattern to obtain the semiconductor device as shown in FIGS. 1A and 1B.
It is generally difficult to position the through-hole 57 strictly above the contact hole 56, as shown in FIG. 1A, because the surface shows significant steps in the vicinity of the contact hole due to the stepped structure therein, so that the through-hole 57 positioned above may not be opened completely or the upper second wiring 52 may be unable to sufficiently cover a step of significant size and may become disconnected.
Also the wiring pattern has to be made with a size overlapping by a certain margin, to the periphery of the contact hole 56, in order that the contact hole 56 is securely covered by the first wiring 51. If the margin is not enough, the aluminum in the contact hole may also be etched in the aluminum etching operation, whereby serious troubles may arise in the contact resistance and in the surface insulation characteristic. A similar situation applies also to the relation between the pattern of the through-hole 57 and the second wiring 52.
Because of the above-mentioned reasons, the wiring area can only be reduced to a certain limit, and the chip size cannot be reduced significantly, with the surface steps therein, in spite of the miniaturization of the constituent elements
The following is an explanation of the producing method of a second conventional example of the semiconductor device, with reference to FIGS. 2B and 2A, which are respectively a plan view of the device and a cross-sectional view along a line A--A' in FIG. 2B.
The method for producing this semiconductor device is similar to that of the first conventional example except for the presence or absence of holes. As FIG. 2A shows only a cross section of twisted pair lines constituting an inductance, a contact hole between a first wiring 71 and a first 10 insulation layer 73 consisting of silicon is not illustrated. In FIG. 2A, the dimensions L1, L2 and L3 are respectively 0.8, 1.4 and 1.0 .mu.m. Also in FIG. 2B, the dimensions L4, L5, L6 and L7 are respectively 3.0, 4.8, 3.0 and 1.0 .mu.m. Since an alignment error in the photolithography results in serious troubles in the connection and reliability of the contacts and the through-holes 76 as in the first conventional example, the dimension of the first and second wirings 71, 72 has to be considerably larger than that of the through-holes 76 (1.4 .mu.m) as shown in FIG. 2B, so that a high level of integration is very difficult to achieve.
Now, the following is an explanation of the method of forming contact between a semiconductor electrode and a silicon substrate, and forming a through-hole in a multi-layered wiring structure in the conventional semiconductor devices, with reference to FIGS. 3 to 6.
FIG. 3 is a cross-sectional view of a structure in which a through-hole TH101 is formed, above a field oxide film 104, in order to connect a first aluminum layer 101 and a second aluminum layer 102. 103 indicates a silicon substrate, and 104 and 105 are SiO.sub.2 films.
In such case, the through-holes can be formed with a minimum size, but such structure is an obstacle to the high level of integration since the connection to the first aluminum layer 101 has to be connected through and overlying field oxide film 106.
FIG. 4 is a cross-sectional view of a through-hole TH102 formed in a relatively thin oxide film 107, instead of the field oxide film. 108 indicates a SiO.sub.2 film. As indicated by dimensions L1, L2, L3, L4, L5 and L6 respectively of 0.4, 0.8, 0.8, 1.6, 0.8 and 4.2 .mu.m, the through-hole has to be sized larger for ensuring a proper aperture for the photolithography because of the height relationship is different from that for the through-hole in the field oxide film. Also the connection to the first aluminum layer has to be established as in the structure shown in FIG. 3.
FIGS. 5 and 6 are cross-sectional views of a through-hole formed on a contact by a first Al layer 101 to the silicon substrate, wherein 109 and 110 indicate SiO.sub.2 films. In FIG. 6, dimensions L7, L8, L9, L10, L11 and L12 are respectively 0.4, 0.8, 0.8, 0.8, 0.4 and 3.2 .mu.m.
In FIG. 5 the through-hole TH103 is larger than the contact hole CH103, while in FIG. 6, the through-hole TH104 is smaller than the contact hole CH104.
In either case a proper hole opening has to be secured by employing different sizes for the contact and through-holes, thereby utilizing a relatively flat area for forming the through-hole.
FIGS. 7A and 7B show a coaxial wiring achieved by a conventional three-layer Al wiring technology, wherein FIG. 7A is a schematic cross-sectional view of the coaxial wiring structure, while FIG. 7B is a plan view thereof. A second aluminum layer 202 is used as a signal line, while a first aluminum layer 201 and a third aluminum layer 203 are used as shield wires and are mutually connected through first through-holes 209, second aluminum layers 202 and second through-holes 210. 204 indicates a SiO.sub.2 substrate. The first aluminum layer 201 and the third aluminum layer 203 are connected to an electrically stable potential (ground potential). In FIG. 7A, dimensions L1, L2, L3 and L4 are respectively 3.2 or 4.2, 1.0, 1.5 and 6.7 or 7.7 .mu.m.
A multi-layered wiring structure as shown in FIGS. 1A, 1B, 2A and 2B, obtained by a conventional multi-layered wiring technology, has been associated with the following drawbacks to be resolved.
The multi-layered wiring structure, intended for increasing the wiring density, has been obtained by laminating an insulation layer (a silicon oxide film) on a first wiring layer, then forming a second wiring layer, and repeating the above-mentioned operations for third and subsequent wiring layers. Thus the structure of wiring is defined by the disconnection or migration of the wirings resulting from surface steps and the form of contact and through holes required for connection through the insulation layer, so that the increase in wiring density has been limited.
For example the contact hole and the first through-hole, or the first through-hole and the second through-hole, have to be mutually displaced, and a sufficient line/space width has to be provided against wiring disconnection or migration resulting from the surface steps.
In the conventional semiconductor devices as shown in FIGS. 3 to 6, there are required very large areas for contact between the semiconductor electrode and the silicon substrate and for the through-hole for connecting the first and second aluminum layers, in order to obtain a sufficiently large flat area, so that a high level of integration has been difficult to achieve. Also wirings with three or more layers have been difficult to realize as the flattening of the entire layer has not be achieved.
Also in the conventional coaxial wiring structure as shown in FIGS. 7A and 7B, in which the shield is composed of the first Al layer 201, first through-hole 209, second Al layer 202, second through-hole 210 and third Al layer 203, the first through hole 209 and the second through-hole 210 have to be formed by patterning the second Al layer 202 as shown in FIG. 7B and have to be mutually displaced.
Also the first Al layer 201, first through-hole 209, second Al layer 202, second through-hole 210 and third Al layer 203 have to so constructed, as shown in FIG. 8, to satisfy a specific relationship [diameter of first through-hole 209]&lt;[diameter of second through-hole 210].
As will be understood from FIGS. 7A, 7B and 8, in the conventional coaxial wiring structure, as the form of the second Al layer 202 is determined by the shapes of the first and second through-holes 209, 210, the density of the signal lines is governed by the shield lines composed of the second Al layer 202.